代码搜索：cannot
找到约 7,468 项符合「cannot」的源代码
代码结果 7,468
www.eeworm.com/read/207820/15261450
c printk.c
/*
* linux/kernel/printk.c
*
* (C) 1991 Linus Torvalds
*/
/*
* When in kernel-mode, we cannot use printf, as fs is liable to
* point to 'interesting' things. Make a printf with fs-saving, an
www.eeworm.com/read/207672/15265143
header en@boldquot.header
# All this catalog "translates" are quotation characters.
# The msgids must be ASCII and therefore cannot contain real quotation
# characters, only substitutes like grave accent (0x60), apostrophe (0x
www.eeworm.com/read/207672/15265150
header en@quot.header
# All this catalog "translates" are quotation characters.
# The msgids must be ASCII and therefore cannot contain real quotation
# characters, only substitutes like grave accent (0x60), apostrophe (0x
www.eeworm.com/read/14814/423866
cpp test.cpp
if((out=fopen("13.txt","w"))==NULL)
{
printf("cannot open the file \n");
exit(0);
}
for(i=0;i
www.eeworm.com/read/16793/691518
header en@boldquot.header
# All this catalog "translates" are quotation characters.
# The msgids must be ASCII and therefore cannot contain real quotation
# characters, only substitutes like grave accent (0x60), apostrophe (0x
www.eeworm.com/read/16793/691544
header en@quot.header
# All this catalog "translates" are quotation characters.
# The msgids must be ASCII and therefore cannot contain real quotation
# characters, only substitutes like grave accent (0x60), apostrophe (0x
www.eeworm.com/read/17761/756518
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONE_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONE_PRIM_DFFE;
www.eeworm.com/read/17761/756823
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONE_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONE_PRIM_DFFE;
www.eeworm.com/read/17761/757198
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONE_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONE_PRIM_DFFE;
www.eeworm.com/read/17761/757574
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONE_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONE_PRIM_DFFE;