代码搜索：buffer

找到约 10,000 项符合「buffer」的源代码

代码结果 10,000
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www.eeworm.com/read/246107/12756077

vi initiate (internal buffer).vi

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www.eeworm.com/read/246107/12756082

vi fetch (internal buffer).vi

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www.eeworm.com/read/332117/12777623

mif buffer_img.mif

11111111 11011000 11111111 11100000 00000000 00010000 01001010 01000110 01001001 01000110 00000000 00000001 00000010 00000000 00000000 00000001 00000000 00000001 00000000 00000000
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www.eeworm.com/read/332117/12777626

coe buffer_img.coe

MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR= FF,D8,FF,E0,00,10,4A,46,49,46,00,01,02,00,00,01,00,01,00,00,FF,C0,00,11,08, 00,00,00,00, 03,01,22,00,02,11,01,03,11,01,FF,DB,00,84
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www.eeworm.com/read/332117/12777629

xco buffer_img.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
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www.eeworm.com/read/332117/12777655

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enab
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www.eeworm.com/read/332117/12777659

xco buffer_comp.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
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www.eeworm.com/read/332117/12777678

edn buffer_img.edn

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 10 11 3 28 17) (author "Xilinx, Inc.") (program "Xilinx CORE Generator" (version "X
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www.eeworm.com/read/332117/12777693

vho buffer_img.vho

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation
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www.eeworm.com/read/332117/12777697

vhd buffer_img.vhd

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation
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