代码搜索：buffer

找到约 10,000 项符合「buffer」的源代码

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www.eeworm.com/read/161671/10387036

h obj_buffer.h

//*---------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //*------------------------------------------------------
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www.eeworm.com/read/161509/10400021

dll lyapunov_buffer.dll

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www.eeworm.com/read/353746/10422750

h harfbuzz-buffer.h

/* * Copyright (C) 1998-2004 David Turner and Werner Lemberg * Copyright (C) 2004,2007 Red Hat, Inc. * * This is part of HarfBuzz, an OpenType Layout engine library. * * Permission is hereby g
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www.eeworm.com/read/353746/10422761

c harfbuzz-buffer.c

/* * Copyright (C) 1998-2004 David Turner and Werner Lemberg * Copyright (C) 2004,2007 Red Hat, Inc. * * This is part of HarfBuzz, an OpenType Layout engine library. * * Permission is hereby g
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www.eeworm.com/read/278956/10486132

dll lyapunov_buffer.dll

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www.eeworm.com/read/160189/10559727

mif buffer_img.mif

11111111 11011000 11111111 11100000 00000000 00010000 01001010 01000110 01001001 01000110 00000000 00000001 00000010 00000000 00000000 00000001 00000000 00000001 00000000 00000000 11111111 11000000 00
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www.eeworm.com/read/160189/10559730

coe buffer_img.coe

MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR= FF,D8,FF,E0,00,10,4A,46,49,46,00,01,02,00,00,01,00,01,00,00,FF,C0,00,11,08, 00,00,00,00, 03,01,22,00,02,11,01,03,11,01,FF,DB,00,84, 00,
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www.eeworm.com/read/160189/10559734

xco buffer_img.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #
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www.eeworm.com/read/160189/10559760

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559762

xco buffer_comp.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #
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