代码搜索：buffer

找到约 10,000 项符合「buffer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/287637/8677403

h obj_buffer.h

//*---------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //*------------------------------------------------------
·
www.eeworm.com/read/287361/8690112

m clear_buffer.m

function clear_buffer global TRJ_bufer Time_bufer bufer_i; bufer_i = 1;
·
www.eeworm.com/read/286738/8746524

c dump_buffer.c

/* * * $Id: dump_buffer.c 133 2005-05-09 17:35:14Z federico $ * * This file is part of Fenice * * Fenice -- Open Media Server * * Copyright (C) 2004 by * * - Giampaolo Mancini
·
www.eeworm.com/read/430383/8752055

mif buffer_img.mif

11111111 11011000 11111111 11100000 00000000 00010000 01001010 01000110 01001001 01000110 00000000 00000001 00000010 00000000 00000000 00000001 00000000 00000001 00000000 00000000 11111111 11000000 00
·
www.eeworm.com/read/430383/8752058

coe buffer_img.coe

MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR= FF,D8,FF,E0,00,10,4A,46,49,46,00,01,02,00,00,01,00,01,00,00,FF,C0,00,11,08, 00,00,00,00, 03,01,22,00,02,11,01,03,11,01,FF,DB,00,84, 00,
·
www.eeworm.com/read/430383/8752060

xco buffer_img.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #
·
www.eeworm.com/read/430383/8752077

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
·
www.eeworm.com/read/430383/8752079

xco buffer_comp.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #
·
www.eeworm.com/read/430383/8752098

edn buffer_img.edn

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 10 11 3 28 17) (author "Xilinx, Inc.") (program "Xilinx CORE Generator" (version "Xili
·
www.eeworm.com/read/430383/8752116

vho buffer_img.vho

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation,
·