代码搜索：asynchronous
找到约 2,366 项符合「asynchronous」的源代码
代码结果 2,366
www.eeworm.com/read/157785/11663034
v mult8x8_s.v
//
// Module: MULT8X8_S
//
// Description: Verilog Sub-module
// 8-bit X 8-bit embedded signed multiplier (asynchronous)
//
// Device: Virtex-II Family
//
// Copyright (c) 2000 Xilinx, Inc. A
www.eeworm.com/read/157785/11663045
v mult8x8_u.v
//
// Module: MULT8X8_U
//
// Description: Verilog Sub-module
// 8-bit X 8-bit embedded unsigned multiplier (asynchronous)
//
// Device: Virtex-II Family
//
// Copyright (c) 2000 Xilinx, Inc.
www.eeworm.com/read/157209/11730181
txt 带load、clr等功能的寄存器.txt
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/253982/12170997
v dram.v
// picdram stands for PIC "Data" RAM.
//
//
// Synchronous Data RAM, 8 bits wide, N words deep.
//
// ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs **
// This is so that we can do a Rea
www.eeworm.com/read/149607/12362871
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/126327/14428571
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2, q3, q4, q5, q6, q7 : O
www.eeworm.com/read/227189/14437626
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/125701/14470245
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/216339/15018875
c usart.c
#define USART_C
#include "iom32.h"
//#define "includes.h"
void usart_putchar(char c)
{
if(c=='\n')
usart_putchar('/r');
while(UCSRA&(1
www.eeworm.com/read/172593/5383738
h ahdlc.h
#ifndef _DEV_AHDLC_H_
#define _DEV_AHDLC_H_
/*
* Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* mod