代码搜索:asynchronous
找到约 2,366 项符合「asynchronous」的源代码
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www.eeworm.com/read/141282/13024741
txt 带load、clr等功能的寄存器.txt
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load
www.eeworm.com/read/327324/13086525
c sio.c
/*
sio (used with feed)
AUP2, Sec. 3.9.8
Copyright 2003 by Marc J. Rochkind. All rights reserved.
May be copied only for purposes and under conditions described
on the Web page www.basepath.com/
www.eeworm.com/read/327324/13086577
cpp uxaio.cpp
/*
Copyright 2003 by Marc J. Rochkind. All rights reserved.
May be copied only for purposes and under conditions described
on the Web page www.basepath.com/aup/copyright.htm.
The Example Files ar
www.eeworm.com/read/322893/13362372
asm cvectors.asm
* Writing to the C2xx Asynchronous Serial Port in C V1.00
* by Jeff Axelrod 3/26/97
.title "vectors.asm"
.ref _c_int0,_nothing,_uart
.sect ".vectors"
reset: b _c_int0
int1: b _nothing
i
www.eeworm.com/read/319921/13439510
txt 带load、clr等功能的寄存器.txt
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/313565/13584793
v dram.v
// picdram stands for PIC "Data" RAM.
//
//
// Synchronous Data RAM, 8 bits wide, N words deep.
//
// ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs **
// This is so that we can do a Rea
www.eeworm.com/read/312754/13605443
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/305986/13755614
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/305054/13779380
txt 带load、clr等功能的寄存器.vhd.txt
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/101082/6244630
8nfs biod.8nfs
.\" SCCSID: @(#)biod.8nfs 8.1 9/11/90
.TH biod 8nfs
.SH Name
biod \- Start NFS asynchronous block I/O daemons
.SH Syntax
.nf
.ft B
.B /etc/biod [\fIndaemons\fP]
.fi
.SH Description
.NXR "biod daemon"