代码搜索：asynchronous

找到约 2,366 项符合「asynchronous」的源代码

代码结果 2,366
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/275774/10796824

h init.h

************************************************************************ *** f206 Memory Mapped Register Definations (On Data–Page or Page1) *******************************************************
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www.eeworm.com/read/417397/10991803

txt 带load、clr等功能的寄存器.txt

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/399935/7821168

vhd reginf.vhd

-- MAX+plus II VHDL Example -- Register Inference -- Copyright (c) 1994 Altera Corporation ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2, q3, q4, q5, q6, q7 : O
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www.eeworm.com/read/199789/7822628

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/198238/7946289

txt 带load、clr等功能的寄存器.txt

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/198238/7946476

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/197597/7984803

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/145313/12736169

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/145059/12754617

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/145008/12756777

v dram.v

// picdram stands for PIC "Data" RAM. // // // Synchronous Data RAM, 8 bits wide, N words deep. // // ** Must support SYNCHRONOUS WRITEs and ASYNCHRONOUS READs ** // This is so that we can do a Rea
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