代码搜索:arithmetic

找到约 7,844 项符合「arithmetic」的源代码

代码结果 7,844
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eqn frequency.map.eqn

--M1_safe_q[7] is INTIGRATOR_FE:inst|lpm_counter:CYCLE_rtl_0|cntr_ia7:auto_generated|safe_q[7] --operation mode is normal M1_safe_q[7]_carry_eqn = M1L41; M1_safe_q[7]_lut_out = M1_safe_q[7] $ (M1
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vhd da.vhd

------------------------------------------------------------------------------- -- Title : Distributed Arithmetic top level -- Project : Arithmetic blocks -------------------------------------
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vhd da.vhd

------------------------------------------------------------------------------- -- Title : Distributed Arithmetic top level -- Project : Arithmetic blocks ----------------------------------
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vhd da_tb.vhd

------------------------------------------------------------------------------- -- Title :Distributed Arithmetic filter test bench -- Project : Arithmetic blocks ------------------------------
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vhd da_tb.vhd

------------------------------------------------------------------------------- -- Title :Distributed Arithmetic filter test bench -- Project : Arithmetic blocks ---------------------------
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eqn trafficlight.map.eqn

--B1_sdata[1] is scan:inst|sdata[1] --operation mode is normal B1_sdata[1]_lut_out = !B1_sdata[1]; B1_sdata[1] = DFFEAS(B1_sdata[1]_lut_out, B1_EN_in, VCC, , B1_sdata[0], , , , ); --M1L3 is
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eqn uart_regs.fit.eqn

--E4_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X2
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eqn uart_regs.map.eqn

--E4_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3] --opera
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eqn tt.map.eqn

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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eqn colorbar.map.eqn

--B1_hsyncint is vga_vl:inst|hsyncint --operation mode is normal B1_hsyncint_lut_out = !E1_safe_q[10] & B1L91 & E1_safe_q[7] $ !B1L31; B1_hsyncint = DFFEAS(B1_hsyncint_lut_out, F1__clk0, rst, , ,