代码搜索：adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/386113/2573284

tcl hdlorder.tcl

project -fileorder D:/924lyj/924/generator_sin.vhd D:/924lyj/924/generator_acc6.vhd D:/924lyj/924/generator_adder.vhd D:/924lyj/924/generator_and2.vhd D:/924lyj/924/generator_mux.vhd D:/924lyj/924/gen
·
www.eeworm.com/read/386113/2573382

eqn rader_hilbert.eqn

--X22_cs_buffer[16] is adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC_X67_Y24_N8 --operation mode is
·
www.eeworm.com/read/386113/2573404

eqn rader_hilbert.fit.eqn

--X42_cs_buffer[16] is adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC_X67_Y8_N8 --operation mode is
·
www.eeworm.com/read/282480/9091004

eqn fft.map.eqn

--F2_result[7] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7] --operation mode is normal F2_result[7]_carry_eqn = F2L51; F2_result[7] =
·
www.eeworm.com/read/375968/9341154

h item_include.h

#include "encoder_3_8.h" #include "test_encoder_3_8.h" //32位数据二选一多路选择器 #include "mux.h" //符号扩展器 #include "imm_extend.h" //指令加法器 #include "adder_pc.h" //branch指令加法器 #include "branch_pc
·
www.eeworm.com/read/266308/7071261

v alu.v

module ALU(A,B,ALUFN,C,RFLAG,WFLAG);//RFLAG为标志寄存器的输出，WFLAG为ALU产生的标志位N,Z,C,O input[31:0] A,B; input[3:0] ALUFN; input[3:0] RFLAG; output[31:0] C; output[3:0] WFLAG; wire[31:0] c_adder,c_logic,c_s
·
www.eeworm.com/read/264378/11317245

v main_programme.v

module sixty_adder(X,Y,sum,clk,rst,sel,muilt_out); input [63:0] X,Y; input [1:0]sel; input clk,rst; output [64:0]sum; output [127:0] muilt_out; reg [63:0]X_reg,Y_reg ; reg [63:0]X_reg0,Y_reg0; re
·
www.eeworm.com/read/223998/14608198

_info

m255 13 cModel Technology dD:\MyWork\Verilog_Design\ModuleFile\Page621\my_adder2 vFIFO_Buffer IEn8haCLH[8VbizPCL8[f@3 VM]@>CLTa>ZN2QTO[Ffz382 dD:\MyWork\My_FIFO_Asy\FIFO_Syn w1183122718 FD:/MyWork/My_
·
www.eeworm.com/read/223784/14617828

_info

m255 13 cModel Technology dD:\MyWork\Verilog_Design\ModuleFile\Page621\my_adder2 vFIFO_Buffer IEn8haCLH[8VbizPCL8[f@3 VM]@>CLTa>ZN2QTO[Ffz382 dD:\MyWork\My_FIFO_Asy\FIFO_Syn w1183122718 FD:/MyWork/My_
·
www.eeworm.com/read/216450/4893305

makefile

# Makefile for lib/float. CC1 = /bin/sh ./FP.compile LIBRARIES = libfp libfp_OBJECTS = \ add_ext.o \ adder.o \ adf4.o \ adf8.o \ cff4.o \ cff8.o \ cfi.o \ cfu.o \ cif4.o \ cif8.o \ cmf4.
·