代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/274276/10879397
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/454493/7388291
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/454493/7388317
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/435744/7785971
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/435744/7786032
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/240876/13189770
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/240876/13189864
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/325597/13195009
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/325597/13195111
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/138605/13228565
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--