代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/271056/11010412
dec fault_cct.dec
-- Components:
-- 06.06.93 adder_1_cell
library ieee;
package fault_circuit_cmpt is
use ieee.std_logic_1164.all;
component fault_circuit
port (
a : in std_ulogic_vector(9 do
www.eeworm.com/read/302704/13828447
txt 用数值积分计算派值.txt
#include
#include
#include
using namespace std;
const unsigned long maxshort=65536l;
const unsigned long multipilier=1194211693l;
const unsigned long adder=12345l;
class
www.eeworm.com/read/252132/12300492
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/252132/12300494
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/415793/11053747
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/415793/11053752
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/377553/9271641
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/180496/9304804
v alucomb.v
`include "Def_StructureParameter.v"
`include "Def_ALUType.v"
`include "BarrelShift.v"
`include "complementary.v"
`include "Adder.v"
module ALUComb(ALUCombResult,
out_Carry,
out_Zero,
o
www.eeworm.com/read/164942/10081191
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆
www.eeworm.com/read/275690/10801258
vhd bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆