代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/318858/3561716
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity adder is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/436447/1848706
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity adder is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/351002/3111668
vhd sn7483.vhd
--*****************************
--* 4 BIT ADDER IC SN7483 *
--* Filename : SN7483 *
--*****************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_un
www.eeworm.com/read/261703/4319762
v pad.v
// This example shows one how to force the
// use of a particular pad type for lucent.
module adder(cout, sum, a, b, cin);
parameter size = 1; /* declare a parameter. default required */
outpu
www.eeworm.com/read/159905/5578254
aspx addvalues.aspx
Sub Button_Click( s As Object, e As EventArgs )
Dim myAdder As New Adder
myAdder.FirstValue = txtVal1.Text
myAdd
www.eeworm.com/read/323875/3507433
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Adder8 is
port(
\out\ : out vl_logic_vector(7 downto 0);
cout : out vl_logic;
\of\ :
www.eeworm.com/read/323875/3507472
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Adder32 is
port(
sum : out vl_logic_vector(31 downto 0);
cout : out vl_logic;
\of\
www.eeworm.com/read/312645/3667200
entries
/adderII_redboot_ROMRAM.ecm/1.2/Sun Sep 21 12:27:58 2003//
/adder_redboot_ROMRAM.ecm/1.2/Sun Sep 21 12:27:58 2003//
D
www.eeworm.com/read/305277/3778796
scala bug0017.scala
class Quantity {
def getValue = 0;
def connect(c: Constraint) = c.newValue;
}
abstract class Constraint(q: Quantity) {
def newValue: Unit;
q connect this
}
class Adder(q: Quantity) e
www.eeworm.com/read/398200/2394041
entries
/adderII_redboot_ROMRAM.ecm/1.2/Sun Sep 21 12:27:58 2003//
/adder_redboot_ROMRAM.ecm/1.2/Sun Sep 21 12:27:58 2003//
D