代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/383822/8915940
hif adder4.hif
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/284185/8955441
vhd 2_adder.vhd
entity adder is
port (
in1 : bit_vector;
in2 : bit_vector;
pout : out bit_vector
);
end adder;
architecture func of adder is
begin
process(in1,in2)
begin
pout
www.eeworm.com/read/284185/8956357
vhd 1_adder.vhd
entity bit_rtl_adder is
port (
in1 : bit_vector;
in2 : bit_vector;
cntl : bit;
pout : out bit_vector
);
end bit_rtl_adder;
architecture func of bit_rtl_adder is
begin
www.eeworm.com/read/284185/8956364
acf 1_adder.acf
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
www.eeworm.com/read/284185/8956368
hif 1_adder.hif
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/186041/8965194
pdf nbit_adder.pdf
www.eeworm.com/read/281861/9128626
vhd adder8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder8 IS
PORT(
cin : IN STD_LOGIC; --进位输入
a,b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --加数
s : OUT STD_LOGIC_VECTOR(7 DO
www.eeworm.com/read/182737/9193547
vhd adder_synth.vhd
----------------------------------------------------------------------
---- ----
---- adder_synth.vhd
www.eeworm.com/read/182737/9193560
vhd adder_e.vhd
----------------------------------------------------------------------
---- ----
---- adder_e.vhd
www.eeworm.com/read/378479/9229739
v adder16.v
`include "adder.v"
module adder16(cout,sum,a,b,cin);
output cout;
parameter my_size=16;
output[my_size-1:0] sum;
input[my_size-1:0] a,b;
input cin;
adder my_adder(cout,sum,a,b,cin);
endmod