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# # sample NMAKE makefile to make libvpi.dll with VisualC++ on Windows # see windows.txt for more details. # SOURCES = \ sci_alu_combinational_vpi.c \ # sci_alu_sequential_

library verilog; use verilog.vl_types.all; entity can_register is generic( width : integer := 8 ); port( data_in : in vl_logic_vector; data_ou

JDF G // Created by Project Navigator ver 1.0 PROJECT I2C DESIGN i2c DEVFAM spartan2e DEVFAMTIME 0 DEVICE xc2s50e DEVICETIME 0 DEVPKG tq144 DEVPKGTIME 0 DEVSPEED -6 DEVSPEEDTIME 0 DEVTOPLE

# XST (Creating Lso File) : i2c_master_top.lso # Check Syntax i2c_master_top.stx # XST (Creating Lso File) : i2c_master_bit_ctrl.lso # Check Syntax i2c_master_bit_ctrl.stx # xst flow : RunXS

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

library verilog; use verilog.vl_types.all; entity cpu_pcounter is port( cnt_out : out vl_logic_vector(12 downto 0); clk : in vl_logic; data_in

library verilog; use verilog.vl_types.all; entity cpu_register is port( data_out : out vl_logic_vector(15 downto 0); clk : in vl_logic; reset

library verilog; use verilog.vl_types.all; entity dac_test_black_box_wrapper is port( din : in vl_logic_vector(17 downto 0); fltsel : in vl_logic;

library verilog; use verilog.vl_types.all; entity stratix_mac_out_internal is generic( operation_mode : string := "output_only"; dataa_width : integer := 36; datab_wi

library verilog; use verilog.vl_types.all; entity stratix_mac_register is generic( data_width : integer := 18 ); port( data : in vl_logic_vector(71 down