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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and3b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxcy_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
ci
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bscan is
generic(
cds_action : string := "ignore"
);
port(
drck : out vl_logic;
idle
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_ii is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_02 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut1_d_mux2 is
end lut1_d_mux2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_43 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor4b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_fibre_chan_1 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_r