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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity testbench is
end testbench;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
end top;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
end top;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
end test;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
end test;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
end test;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
end top;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity testbed is
end testbed;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity testbed is
end testbed;
i2c.prj
verilog work i2c_clk.v
verilog work i2c_st.v
verilog work i2c.v