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build_vpi_xl.mak
#
# sample NMAKE makefile to make libvpi.dll with VisualC++ on Windows
# see windows.txt for more details.
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = \
show_all_nets_vpi.c \
timescale_info_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
timescale_info_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 7, 1999 02:55:57
Verilog_XL_Turbo_NT 2.6.9 Jan
use_workarea_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
use_workarea_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 30, 1998 12:13:27
Verilog_XL_Turbo_NT 2.6.9 Nov 3
build_vpi_xl.mak
#
# sample NMAKE makefile to make libvpi.dll with VisualC++ on Windows
# see windows.txt for more details.
#
SOURCES = \
# use_workarea_vpi.c \
# read_test_vector_vpi.c \
#
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity control_interface is
port(
clk : in vl_logic;
reset_n : in vl_logic;
cmd : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity int2alaw is
port(
clk : in vl_logic;
law16_int : in vl_logic_vector(15 downto 0);
alaw
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ulaw2int is
port(
clk : in vl_logic;
ulaw : in vl_logic_vector(7 downto 0);
law16_int
lex.yy.c
/* A lexical scanner generated by flex */
/* Scanner skeleton version:
* $Header: /home/daffy/u0/vern/flex/RCS/flex.skl,v 2.91 96/09/10 16:58:48 vern Exp $
*/
#define FLEX_SCANNER
#define YY_FLEX_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cpu_mem is
port(
data_inout : inout vl_logic_vector(15 downto 0);
addr : in vl_logic_vector(12 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cpu_sctrl is
generic(
hlt : integer := 0;
skz : integer := 1;
add : integer := 2;