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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_iii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_ii_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_iii_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_iii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl2_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_i_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl3_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i