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library verilog; use verilog.vl_types.all; entity apex20k_lcell_register is generic( operation_mode : string := "normal"; packed_mode : string := "false"; power_up

library verilog; use verilog.vl_types.all; entity apex20k_pterm is generic( operation_mode : string := "normal"; output_mode : string := "comb"; invert_pterm1_mode:

library verilog; use verilog.vl_types.all; entity apex20k_asynch_mem is generic( logical_ram_depth: integer := 2048; infile : string := "none"; address_width :

library verilog; use verilog.vl_types.all; entity apex20k_asynch_lcell is generic( operation_mode : string := "normal"; output_mode : string := "reg_and_comb"; lut_m

library verilog; use verilog.vl_types.all; entity apex20k_io is generic( operation_mode : string := "input"; reg_source_mode : string := "none"; feedback_mode : string

library verilog; use verilog.vl_types.all; entity oper_mult is generic( width_a : integer := 32; width_b : integer := 32; width_o : integer := 32;

library verilog; use verilog.vl_types.all; entity oper_addsub is generic( width_a : integer := 32; width_b : integer := 32; width_o : integer := 32;

library verilog; use verilog.vl_types.all; entity oper_add is generic( width_a : integer := 32; width_b : integer := 32; width_o : integer := 32;

library verilog; use verilog.vl_types.all; entity oper_bus_mux is generic( width_a : integer := 6; width_b : integer := 6; width_o : integer := 6

library verilog; use verilog.vl_types.all; entity stratixgx_mac_mult_internal is generic( dataa_width : integer := 18; datab_width : integer := 18; dataout_width