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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex6k_lcell_register is
generic(
operation_mode : string := "normal";
packed_mode : string := "false";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex6k_asynch_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
lut_ma
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex10ke_ram_slice is
generic(
operation_mode : string := "single_port";
logical_ram_name: string := "ram_xxx";
logical
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex10ke_asynch_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
lut_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex10ke_asynch_mem is
generic(
logical_ram_depth: integer := 2048;
infile : string := "none";
address_width :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_cam_slice is
generic(
operation_mode : string := "encoded_address";
logical_cam_name: string := "cam_xxx";
logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_hssi_pll is
generic(
clk0_multiply_by: integer := 1;
clk1_divide_by : integer := 1;
input_frequency : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_cam_slice is
generic(
operation_mode : string := "single_match";
logical_cam_name: string := "cam_xxx";
logical
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_asynch_sexp is
port(
datain : in vl_logic_vector(51 downto 0);
dataout : out vl_logic
);
end max_a
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_mcell is
generic(
operation_mode : string := "normal";
output_mode : string := "comb";
register_mode : string