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library verilog; use verilog.vl_types.all; entity stratix_mac_mult_internal is generic( dataa_width : integer := 18; datab_width : integer := 18; dataout_width :

library verilog; use verilog.vl_types.all; entity alt3pram is generic( width : integer := 1; widthad : integer := 1; numwords : integer := 0;

library verilog; use verilog.vl_types.all; entity altshift_taps is generic( number_of_taps : integer := 4; tap_distance : integer := 3; width : integer := 8;

library verilog; use verilog.vl_types.all; entity hssi_tx is generic( channel_width : integer := 1 ); port( clk : in vl_logic; datain : i

library verilog; use verilog.vl_types.all; entity altlvds_tx is generic( number_of_channels: integer := 1; deserialization_factor: integer := 4; registered_input: string :

library verilog; use verilog.vl_types.all; entity dcfifo is generic( lpm_width : integer := 1; lpm_widthu : integer := 1; lpm_numwords : integer := 2;

library verilog; use verilog.vl_types.all; entity altsqrt is generic( q_port_width : integer := 1; r_port_width : integer := 1; width : integer := 1;

library verilog; use verilog.vl_types.all; entity hssi_pll is generic( clk0_multiply_by: integer := 1; clk1_divide_by : integer := 1; input_frequency : integer := 1000

library verilog; use verilog.vl_types.all; entity hssi_fifo is generic( channel_width : integer := 1 ); port( datain : in vl_logic_vector; clk0

library verilog; use verilog.vl_types.all; entity stratixgx_hssi_rx_a1a2_patdet is port( clk : in vl_logic; softreset : in vl_logic; sync_comp_eq