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library verilog; use verilog.vl_types.all; entity wb_mast is generic( mem_size : integer := 4096 ); port( clk : in vl_logic; rst

library verilog; use verilog.vl_types.all; entity wb_slv is generic( mem_size : integer := 13 ); port( clk : in vl_logic; rst : i

library verilog; use verilog.vl_types.all; entity wb_mast is generic( mem_size : integer := 4096 ); port( clk : in vl_logic; rst

library verilog; use verilog.vl_types.all; entity wb_slv is generic( mem_size : integer := 13 ); port( clk : in vl_logic; rst : i

library verilog; use verilog.vl_types.all; entity apex20ke_pterm is generic( operation_mode : string := "normal"; output_mode : string := "comb"; invert_pterm1_mode:

library verilog; use verilog.vl_types.all; entity apex20ke_asynch_lcell is generic( operation_mode : string := "normal"; output_mode : string := "reg_and_comb"; lut_

library verilog; use verilog.vl_types.all; entity apex20ke_ram_slice is generic( operation_mode : string := "single_port"; deep_ram_mode : string := "off"; logical_ram

library verilog; use verilog.vl_types.all; entity apex20ke_asynch_mem is generic( logical_ram_depth: integer := 2048; infile : string := "none"; address_width :

library verilog; use verilog.vl_types.all; entity apex20ke_cam_slice is generic( operation_mode : string := "encoded_address"; logical_cam_name: string := "cam_xxx"; log

library verilog; use verilog.vl_types.all; entity apex20ke_lcell_register is generic( operation_mode : string := "normal"; packed_mode : string := "false"; power_up