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library verilog; use verilog.vl_types.all; entity lpm_compare is generic( lpm_width : integer := 1; lpm_representation: string := "UNSIGNED"; lpm_pipeline : integ

library verilog; use verilog.vl_types.all; entity oper_addsub is generic( width_a : integer := 32; width_b : integer := 32; width_o : integer := 32;

library verilog; use verilog.vl_types.all; entity dcfifo is generic( lpm_width : integer := 1; lpm_widthu : integer := 1; lpm_numwords : integer := 2;

library verilog; use verilog.vl_types.all; entity lpm_divide is generic( lpm_widthn : integer := 1; lpm_widthd : integer := 1; lpm_nrepresentation: string := "UN

library verilog; use verilog.vl_types.all; entity lpm_bustri is generic( lpm_width : integer := 1; lpm_type : string := "lpm_bustri"; lpm_hint : string

library verilog; use verilog.vl_types.all; entity lpm_ram_dq is generic( lpm_width : integer := 1; lpm_widthad : integer := 1; lpm_indata : string := "REGIS

library verilog; use verilog.vl_types.all; entity altsqrt is generic( q_port_width : integer := 1; r_port_width : integer := 1; width : integer := 1;

library verilog; use verilog.vl_types.all; entity n_cntr is port( clk : in vl_logic; reset : in vl_logic; cout : out vl_logic;

library verilog; use verilog.vl_types.all; entity hssi_pll is generic( clk0_multiply_by: integer := 1; clk1_divide_by : integer := 1; input_frequency : integer := 1000

library verilog; use verilog.vl_types.all; entity hcstratix_mac_mult_internal is generic( dataa_width : integer := 18; datab_width : integer := 18; dataout_width