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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity capture_spartan2 is
generic(
cds_action : string := "ignore"
);
port(
cap : in vl_logic;
clk
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_iv_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_33 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_06 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo