代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_output
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_asynch_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
multi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_sexp is
port(
datain : in vl_logic_vector(51 downto 0);
dataout : out vl_logic
);
end max_sexp;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_asynch_mcell is
generic(
operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20k_pll is
generic(
clk0_multiply_by: integer := 1;
clk1_multiply_by: integer := 1;
input_frequency : integer := 1000
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20k_asynch_pterm is
generic(
operation_mode : string := "normal";
invert_pterm1_mode: string := "false"
);
port(
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_dec_6b is
port(
datain : in vl_logic_vector(5 downto 0);
k28 : out vl_logic;
dataout