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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity counter16 is
port(
reset_n : in vl_logic;
clk_in : in vl_logic;
clk16_out : out vl_logic
readme
These files may be used to test the Verilog files generated by Synopsys CoCentric SystemC Compiler.
----------------------------
alfoltran@opencores.org
repository
usb_funct/bench/verilog
entries
D/verilog////
repository
usb_funct/rtl/verilog
entries
D/verilog////
repository
usb_funct/bench/verilog
repository
usb_funct/rtl/verilog
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity spi_top is
generic(
max1 : integer := 8;
max2 : integer := 8;
st0 : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity spi_tb is
generic(
max : integer := 8
);
end spi_tb;