代码搜索结果

m255 cModel Technology dE:\刘韬\MY_WORK\FPGA\程序\I2C vglbl I;3bdO6U;R_i?oXm0zZ=6m3 V]6_PH00iDgcD`AVz9`gA:0 w1059855545 FC:/Program Files/Xilinx/verilog/src/glbl.v L0 5 OE;L;5.7e;17 r1 31 vi2c_slave_model

Selecting top level module demo_amba Synthesizing module qmipsesp Synthesizing module hsckmux Synthesizing module gclkbuff_25um Synthesizing module ahb_master @W:"\\Judd_ql_dallas\D\mips\ahb\inte

library verilog; use verilog.vl_types.all; entity apex20ke_asynch_pterm is generic( operation_mode : string := "normal"; invert_pterm1_mode: string := "false" ); port(

library verilog; use verilog.vl_types.all; entity stratix_ram_register is generic( data_width : integer := 144; sclr : string := "true"; preset :

library verilog; use verilog.vl_types.all; entity alt_exc_dpram is generic( operation_mode : string := "SINGLE_PORT"; addrwidth : integer := 14; width : i

library verilog; use verilog.vl_types.all; entity stratixgx_dec_6b is port( datain : in vl_logic_vector(5 downto 0); k28 : out vl_logic; dataout

library verilog; use verilog.vl_types.all; entity stratixgx_rx_core is generic( channel_width : integer := 10; use_double_data_mode: string := "false"; use_channel_align

library verilog; use verilog.vl_types.all; entity stratixgx_comp_fifo_sm is generic( \IDLE\ : integer := 0; \START\ : integer := 1; \STREAM\ : integ

library verilog; use verilog.vl_types.all; entity flex10ke_pll is generic( clk0_multiply_by: integer := 1; clk1_multiply_by: integer := 1; input_frequency : integer := 1000

library verilog; use verilog.vl_types.all; entity apexii_lcell is generic( operation_mode : string := "normal"; output_mode : string := "reg_and_comb"; packed_mode