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Verilog 的代码
alu_vlog.gfl
# Synplify flow : synCreateProject
__projnav/__synProj.rsp
alu.prj
__projnav/alu.ise_created
alu_compile.tcl
alu_map.tcl
# files created during Synthesis
stdout.log
stderr.log
alu.srs
alu.sr
door_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
_info
m255
cModel Technology
dE:\刘韬\MY_WORK\FPGA\程序\I2C
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
w1059855545
FC:/Program Files/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7e;17
r1
31
vi2c_slave_model
top_zoumigong.prj
verilog work "div_clk_25Mhz.v"
vhdl work "vga.vhd"
verilog work "div16.v"
verilog work "mux2_1_6bits.v"
verilog work "rom_labirint.v"
vhdl work "rom2_labirint.vhd"
verilog work "select_rom.v"
v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity inctl is
generic(
WAIT_DATA : integer := 0;
WAIT_REQ : integer := 1;
TEST : integer := 3;
voptqsz2aa
library verilog;
use verilog.vl_types.all;
entity wb_conbus_arb is
generic(
grant0 : integer := 0;
grant1 : integer := 1;
grant2 : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity wb_conbus_arb is
generic(
grant0 : integer := 0;
grant1 : integer := 1;
grant2 : integer := 2;