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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_add_sub is
generic(
lpm_width : integer := 1;
lpm_representation: string := "SIGNED";
lpm_direction : string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_crcblock is
generic(
oscillator_divider: integer := 1;
lpm_type : string := "stratix_crcblock"
);
port(
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_crcblock is
generic(
oscillator_divider: integer := 1;
lpm_type : string := "hcstratix_crcblock"
);
port
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity arm_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity a_graycounter is
generic(
width : integer := 3;
pvalue : integer := 0;
lpm_type : string := "a_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alt_exc_dpram is
generic(
operation_mode : string := "SINGLE_PORT";
addrwidth : integer := 14;
width : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset