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Verilog 的代码
muxewave_bencher.prj
verilog work D:/Xilinx/verilog/src/glbl.v
gykwave_bencher.prj
verilog work D:/Xilinx/verilog/src/glbl.v
run_lint
#!/bin/sh
nLint \
../../rtl/verilog/or1200_alu.v \
../../rtl/verilog/or1200_amultp2_32x32.v \
../../rtl/verilog/or1200_cfgr.v \
../../rtl/verilog/or1200_cpu.v \
../../rtl/verilog/or1200_ctrl.v \
../..
anal.info
file {
.version = 1;
entity {
.name = "MainU";
.mra_file = "MainU.mra";
.arch = {"verilog"};
.syn_files = {"MainU%verilog.syn", "MainU%verilog__verilog.syn"};
param { .n
sim_file_list.lst
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/wb_slave_behavioral.v
../../../bench/verilog/camera_bench_top.v
make.txt
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/ve
make
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/ve
make
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/ve
make
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/ve
compileformti
#!/bin/csh -f
if (-e work) then
\rm -rf work
endif
vlib work
vlog \
-v ../verilog/src/mem.v \
../verilog/RTL/TopModule.v \
../verilog/RTL/ALUB.v \
../verilog/RTL/CCU.v \
../verilog/FSM/master.v