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Verilog 的代码
vlog.opt
+incdir+../../../../bench/verilog
+incdir+../../../../rtl/verilog
vlog.opt
+incdir+../../../../bench/verilog
+incdir+../../../../rtl/verilog
prescale_counter.prj
verilog work "../source/Verilog/prescale_counter.v"
vlog.opt
+incdir+../../../../bench/verilog
+incdir+../../../../rtl/verilog
parser.xs
#/* Verilog.xs -- Verilog Booter -*- C++ -*-
#*********************************************************************
#*
#* DESCRIPTION: Verilog::Parser Perl XS interface
#*
#* Author: Wilson Snyder
vgavga.prj
verilog work "my_dcm.v"
verilog work "hvsync_generator.v"
verilog work "vgavga.v"
lcd1602.prj
verilog work "DIV16.v"
verilog work "lcd.v"
verilog work "lcd1602.vf"
ddr_tx_test.prj
verilog work "DDR_TX.v"
verilog work "PLL_tx.v"
verilog work "DDR_TX_TOP.v"
verilog work "DDR_TX_TEST.v"
anal.info
file {
.version = 1;
entity {
.name = "adder";
.mra_file = "adder.mra";
.arch = {"verilog"};
.syn_files = {"adder%verilog.syn", "adder%verilog__verilog.syn"};
}
}
rtl_file_list.lst
../../../rtl/verilog/camera_async_reset_flop.v
../../../rtl/verilog/camera_cb_table.v
../../../rtl/verilog/camera_cr_table.v
../../../rtl/verilog/camera_fifo.v
../../../rtl/verilog/camera_fifo_ctrl.v