代码搜索结果
找到约 10,000 项符合
Verilog 的代码
nc.scr
+libext+.v
+access+wr
+mess
+incdir+../../../rtl/verilog+../../../bench/verilog
+tcl+../bin/sim.tcl
-y ../../../rtl/verilog
-y ../../../bench/verilog
../../../bench/verilog/uart_test.v
//+gui
sim_file_list.lst
../../../bench/verilog/tb_ethernet.v
../../../bench/verilog/tb_eth_defines.v
../../../bench/verilog/eth_phy.v
../../../bench/verilog/eth_phy_defines.v
../../../bench/verilog/wb_bus_mon.v
../../..
nc.scr
+libext+.v
+access+wr
+mess
+incdir+../../../rtl/verilog+../../../bench/verilog
+tcl+../bin/sim.tcl
-y ../../../rtl/verilog
-y ../../../bench/verilog
../../../bench/verilog/uart_test.v
//+gui
preproc.xs
#/* Verilog.xs -- Verilog Booter -*- C++ -*-
#*********************************************************************
#*
#* DESCRIPTION: Verilog::Preproc Perl XS interface
#*
#* Author: Wilson Snyder
eexy.prj
verilog work "../complexmul.v"
verilog work "../cutbit/jiewei.v"
verilog work "eexy.v"
muxe.prj
verilog work "../complexmul.v"
verilog work "../cutbit/jiewei.v"
verilog work "muxe.v"
test_bencher.prj
verilog work "freque.v"
verilog work D:/Xilinx9.1/verilog/src/glbl.v
char_generator.prj
verilog work "rom_empty_char.v"
verilog work "rom_human_char.v"
verilog work "rom_wall_char.v"
verilog work "rom_door_char.v"
verilog work "mux8_1_3bits.v"
verilog work "char_generator.v"
make
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_
make
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_