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library verilog; use verilog.vl_types.all; entity obuft_u is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity startup_virtex is generic( cds_action : string := "ignore" ); port( clk : in vl_logic; gsr

library verilog; use verilog.vl_types.all; entity srlc16 is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q

library verilog; use verilog.vl_types.all; entity iobuf_f_2 is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity or2b1 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i0

library verilog; use verilog.vl_types.all; entity ramb16_s1_s9 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : integer

library verilog; use verilog.vl_types.all; entity ofdi_s_24 is generic( cds_action : string := "ignore"; init : integer := 1 ); port( q

library verilog; use verilog.vl_types.all; entity obuf_lvcmos18_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_hstl_i_dci_18 is generic( cds_action : string := "ignore" ); port( o : out vl_logic;

library verilog; use verilog.vl_types.all; entity ibufds_blvds_25 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i