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Verilog 的代码
my_strobe_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_strobe_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 2, 1998 23:06:46
Verilog_XL_Turbo_NT 2.6.9 Dec 2,
sci_alu_sequential_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_sequential_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 01:19:34
Verilog_XL_Turbo_NT 2.6.9
sci_alu_with_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_with_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 04:15:19
Verilog_XL_Turbo_NT 2.6.9
sci_alu_combinational_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_combinational_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 15:27:19
Verilog_XL_Turbo_NT 2.6.
sci_alu_sequential_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_sequential_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 15:29:47
Verilog_XL_Turbo_NT 2.6.9
sci_alu_with_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_with_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 15:38:02
Verilog_XL_Turbo_NT 2.6.9
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_crc is
generic(
tp : integer := 1
);
port(
clk : in vl_logic;
data : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sdr_sdram is
port(
clk : in vl_logic;
reset_n : in vl_logic;
addr : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll1 is
port(
inclock : in vl_logic;
locked : out vl_logic;
clock0 : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity command is
port(
clk : in vl_logic;
reset_n : in vl_logic;
saddr : in vl_logic_v