代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s4_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s8_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ibufds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity regcevht is
generic(
port_width : integer := 8
);
port(
d : in vl_logic_vector;
c
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_b_notc_v2 is
port(
a_in : in vl_logic;
b_in : in vl_logic;
c_in : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tsb16xvht is
generic(
output_width : integer := 8
);
port(
sdi : in vl_logic;
c :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity adrlevht is
generic(
input_width : integer := 8;
signed : integer := 1
);
port(
a : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_b_notc_v4 is
port(
a_in : in vl_logic;
b_in : in vl_logic;
c_in : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity adrevht is
generic(
input_width : integer := 8;
signed : integer := 1
);
port(
a : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_flip_flop_v2_0 is
generic(
zero_string : integer := 0
);
port(
d : in vl_logic;
clk