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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s2_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s1_s2 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s1_s1 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s8_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s4_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s4_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s2 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_mult18x18s is
port(
p : out vl_logic_vector(35 downto 0);
a : in vl_logic_vector(17 downto 0)
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_obuftds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob