代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufsn_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity capture_virtex is
generic(
cds_action : string := "ignore"
);
port(
cap : in vl_logic;
clk
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s1_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s1_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s1_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s2_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s4 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_obufds is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s2_s2 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s2_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : intege