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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x1d is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldcp_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_s_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clkdllhf is
generic(
clkdv_divide : real := 2.000000;
duty_cycle_correction: string := "TRUE";
factory_jf : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufn_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl2_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v