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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_s_8 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufdn_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_s is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_lvpecl is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_flag is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end c_flag;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity capture_virtex2 is
generic(
cds_action : string := "ignore"
);
port(
cap : in vl_logic;
clk
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufds_blvds_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos18_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_ctt is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i