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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos33_f_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos33_f_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos33_s_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_sstl2_i is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos33_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos15_f_12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_pci66_3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuftds_blvds_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and5b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0