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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos15_s_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_s_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_f_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_flag is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end x_flag;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifd_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos15_f_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity xorcy_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos18_f_2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_f_12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i