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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_pterm_register is
generic(
power_up : string := "low"
);
port(
datain : in vl_logic;
c
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
packed_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram7x20_syn is
generic(
ram_width : integer := 20
);
port(
wclk : in vl_logic;
rst_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b6mux21 is
port(
\MO\ : out vl_logic_vector(5 downto 0);
\A\ : in vl_logic_vector(5 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20k_pterm_register is
generic(
power_up : string := "low"
);
port(
datain : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity carry_sum is
port(
cin : in vl_logic;
sum_in : in vl_logic;
cout : out vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_asmiblock is
port(
dclkin : in vl_logic;
scein : in vl_logic;
sdoin : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);