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library verilog; use verilog.vl_types.all; entity iobufd_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos15_s_12 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity ramb16_s4_s4 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : integer

library verilog; use verilog.vl_types.all; entity fdr_1 is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q :

library verilog; use verilog.vl_types.all; entity iobufnd_f is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity iobuf_n_f is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity obuf_f_8 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_lvttl_s_8 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ibuf_lvdci_18 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ibufg_sstl2_ii_dci is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i