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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofddrcpe is
port(
q : out vl_logic;
c0 : in vl_logic;
c1 : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_gtlp is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity xnor5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fddrcpe is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor4b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x8s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bscan_virtex is
generic(
cds_action : string := "ignore"
);
port(
tdo1 : in vl_logic;
tdo2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_sstl3_i is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen_s is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :