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Verilog 的代码
rtl_file_list.lst
../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../
rtl_file_list.lst
../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../
rtl_file_list.lst
../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../
rtl_file_list.lst
../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../
rtl_file_list.lst
../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../
sim_file_list.lst
../../../../bench/verilog/tb_ethernet.v
../../../../bench/verilog/tb_eth_defines.v
../../../../bench/verilog/eth_phy.v
../../../../bench/verilog/eth_phy_defines.v
../../../../bench/verilog/wb_bus_
sim_file_list.lst
../../../../bench/verilog/tb_ethernet.v
../../../../bench/verilog/tb_eth_defines.v
../../../../bench/verilog/eth_phy.v
../../../../bench/verilog/eth_phy_defines.v
../../../../bench/verilog/wb_bus_
initial1_stx.prj
verilog work "initial1.v"
verilog work D:/Xilinx/verilog/src/glbl.v
initial1.isim_stx_prj
verilog work "initial1.v"
verilog work D:/Xilinx/verilog/src/glbl.v
make_fpga
verilog ../../../syn/src/verilog/oc8051_fpga_top.v ../../../bench/verilog/oc8051_fpga_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_