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library verilog; use verilog.vl_types.all; entity fdcp_1 is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q

library verilog; use verilog.vl_types.all; entity onand2 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i0

library verilog; use verilog.vl_types.all; entity obufn_24 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobufnn_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_lo

library verilog; use verilog.vl_types.all; entity iobuf_f_6 is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity obuf_lvcmos33_s_2 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_lvcmos33_f_8 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobuf_pcix is port( o : out vl_logic; io : inout vl_logic; i : in vl_logi

library verilog; use verilog.vl_types.all; entity obuft_lvttl_f_16 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_lvcmos33_f_24 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i