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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_fibre_chan_2 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_r
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdxi_m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxcy_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdx_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtxi_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdxi_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdxi_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q