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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_sstl2_ii_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffx_m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup_virtex is
generic(
cds_action : string := "ignore"
);
port(
clk : in vl_logic;
gsr
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_u is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fmap_puc is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxcy_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
ci
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_fibre_chan_1 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_r