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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx_m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_fibre_chan_4 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_r
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult_and is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup_spartan2 is
generic(
cds_action : string := "ignore"
);
port(
clk : in vl_logic;
gsr