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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffx_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtxi_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fmap_plc is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup_virtex2 is
generic(
cds_action : string := "ignore"
);
port(
clk : in vl_logic;
gsr
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdxi_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx_fu is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q